Senior DFT Design/micro Architect Engineer, Google Cloud
Senior Dft Design/Micro Architect Engineer
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for the next generation System on a Chip (SoCs). You will design, insert, and verify the DFT logic. You will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield.
Responsibilities:
- Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for High speed IOs, Analog DFT).
- Develop and drive die level DFT validation strategy and complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
- Integrate DFT logic, boundary scan, scan chains, DFT compression, Logic BIST, TAP controller, clock control block, and other DFT IP blocks.
- Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
- Generate and deliver the production and debug patterns to Post Silicon Engineering team and run diagnosis for post silicon supports.